iverilog (science/iverilog) Updated: 2 years, 5 months ago Add to my watchlist
Icarus VerilogIcarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format.
Version: 11.0 License: GPL-2+ GitHubMaintainers | padf |
Categories | science |
Homepage | http://iverilog.icarus.com/ |
Platforms | darwin |
Variants | - |
"iverilog" depends on
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Livecheck results
iverilog seems to have been updated (port version: 11_0, new version: 12_0)
livecheck ran: 8 hours ago