iverilog (science/iverilog) Updated: 2 years, 5 months ago Add to my watchlist
Icarus VerilogIcarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format.
Version: 11.0 License: GPL-2+ GitHubStatistics for selected duration
2024-Apr-03 to 2024-May-03
Total Installations | 9 |
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Requested Installations | 4 |
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