veryl (lang/veryl) Updated: 1 month, 3 weeks ago Add to my watchlist
Veryl: A Modern Hardware Description LanguageVeryl: A Modern Hardware Description Language. Veryl is designed as a "SystemVerilog Alternative". There are some design concepts: it has a simplified syntax based on SystemVerilog/Rust, transpiles to SystemVerilog, generates human-readable SystemVerilog code, and comes with integrated tools like a formatter/linter, and integrates with VSCode.
Version: 0.8.1 License: (Apache-2 or MIT)
GitHub
| Maintainers | herbygillot |
| Categories | lang |
| Homepage | https://github.com/veryl-lang/veryl |
| Platforms | darwin |
| Variants |
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veryl seems to have been updated (port version: 0.8.1, new version: 0.9.0)
livecheck ran: 15 hours ago