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Veryl: A Modern Hardware Description Language

Veryl: A Modern Hardware Description Language. Veryl is designed as a "SystemVerilog Alternative". There are some design concepts: it has a simplified syntax based on SystemVerilog/Rust, transpiles to SystemVerilog, generates human-readable SystemVerilog code, and comes with integrated tools like a formatter/linter, and integrates with VSCode.

Version: 0.8.1 License: (Apache-2 or MIT) GitHub
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18 build(s) found
Builder Build Number Start Time Elapsed Time Watcher Build Status
10.7 181283 2024-03-20 23:06:57 0:00:33 55905 failed install-dependencies
10.14 199429 2024-03-18 23:01:10 0:20:28 65192 build successful
10.8 168598 2024-03-18 18:30:10 0:00:27 53966 failed install-dependencies
10.13 224630 2024-03-18 14:41:22 0:21:52 74441 build successful
12 100339 2024-03-17 12:09:52 0:27:16 32925 build successful
10.10 260179 2024-03-16 17:10:31 0:00:25 83489 failed install-dependencies
14 32653 2024-03-16 10:03:58 0:15:59 6982 build successful
13 64020 2024-03-15 22:52:55 0:14:35 18801 build successful
10.15 175443 2024-03-15 13:18:46 0:19:17 54182 build successful
12.arm64 120620 2024-03-15 9:05:29 0:04:42 32909 build successful
13.arm64 52888 2024-03-15 7:06:16 0:04:38 18540 build successful
14.arm64 20309 2024-03-15 3:59:14 0:04:44 6653 build successful
11 146397 2024-03-15 3:36:40 0:18:18 44111 build successful
10.6 157245 2024-03-15 3:00:34 0:00:26 56128 failed install-dependencies
10.9 267205 2024-03-15 2:45:21 0:00:26 83173 failed install-dependencies
10.11 255084 2024-03-15 2:42:48 0:00:27 83597 failed install-dependencies
10.6.x86_64 192871 2024-03-15 2:38:33 0:00:20 56174 failed install-dependencies
10.12 264417 2024-03-15 2:27:34 0:20:01 82383 build successful