{"name":"veryl","portdir":"lang/veryl","version":"0.19.1","license":"(Apache-2 or MIT)","platforms":"darwin","epoch":0,"replaced_by":null,"homepage":"https://github.com/veryl-lang/veryl","description":"Veryl: A Modern Hardware Description Language","long_description":"Veryl: A Modern Hardware Description Language. Veryl is designed as a \"SystemVerilog Alternative\". There are some design concepts: it has a simplified syntax based on SystemVerilog/Rust, transpiles to SystemVerilog, generates human-readable SystemVerilog code, and comes with integrated tools like a formatter/linter, and integrates with VSCode.","active":true,"categories":["lang"],"maintainers":[{"name":"herby.gillot","github":"herbygillot","ports_count":1064}],"variants":["universal"],"dependencies":[{"type":"build","ports":["cargo","legacy-support","rust","clang-20"]},{"type":"fetch","ports":["git"]},{"type":"lib","ports":["libunwind"]}],"depends_on":[]}