veryl (lang/veryl) Updated: 3 weeks, 6 days ago Add to my watchlist
Veryl: A Modern Hardware Description LanguageVeryl: A Modern Hardware Description Language. Veryl is designed as a "SystemVerilog Alternative". There are some design concepts: it has a simplified syntax based on SystemVerilog/Rust, transpiles to SystemVerilog, generates human-readable SystemVerilog code, and comes with integrated tools like a formatter/linter, and integrates with VSCode.
Version: 0.13.3 License: (Apache-2 or MIT)
GitHub
| Maintainers | herbygillot |
| Categories | lang |
| Homepage | https://github.com/veryl-lang/veryl |
| Platforms | darwin |
| Variants |
|
"veryl" depends on
lib (1)
build (4)
fetch (1)
Ports that depend on "veryl"
No ports
Port Health:
Loading Port Health