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VeriWell Verilog Simulator

VeriWell is a full Verilog simulator. It supports nearly all of the IEEE1364-1995 standard, as well as PLI 1.0. VeriWell is the same simulator that was sold by Wellspring Solutions in the mid-1990 and was included with the Thomas and Moorby book

Version: 2.8.7 License: GPL-2+ GitHub
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Categories science
Platforms darwin
  • universal (Build for multiple architectures)

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