GET /api/v1/ports/veriwell/
HTTP 200 OK
Allow: GET, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "name": "veriwell",
    "portdir": "science/veriwell",
    "version": "2.8.7",
    "license": "GPL-2+",
    "platforms": "darwin",
    "epoch": 0,
    "replaced_by": null,
    "homepage": "http://sourceforge.net/projects/veriwell",
    "description": "VeriWell Verilog Simulator",
    "long_description": "VeriWell is a full Verilog simulator. It supports nearly all of the IEEE1364-1995 standard, as well as PLI 1.0. VeriWell is the same simulator that was sold by Wellspring Solutions in the mid-1990 and was included with the Thomas and Moorby book",
    "active": true,
    "categories": [
        "science"
    ],
    "maintainers": [],
    "variants": [
        "universal"
    ],
    "dependencies": [
        {
            "type": "build",
            "ports": [
                "clang-9.0",
                "help2man"
            ]
        },
        {
            "type": "lib",
            "ports": [
                "bzip2",
                "zlib",
                "readline"
            ]
        }
    ],
    "depends_on": []
}