verilator (science/verilator) Updated: 2 months, 1 week ago Add to my watchlist
Verilog compiler and simulatorVerilator is a Verilog compiler and simulator.
Version: 5.028 License: (LGPL-3 or Artistic-2)
GitHub
| Maintainers | MarcusCalhoun-Lopez |
| Categories | science electronics |
| Homepage | https://github.com/verilator/verilator |
| Platforms | darwin |
| Variants |
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"verilator" depends on
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Livecheck results
verilator seems to have been updated (port version: 5.028, new version: 5.030)
livecheck ran: 12 hours ago