verilator (science/verilator) Updated: 6 months, 3 weeks ago Add to my watchlist
Verilog compiler and simulatorVerilator is a Verilog compiler and simulator.
Version: 5.028 License: (LGPL-3 or Artistic-2)
GitHub
| Maintainers | MarcusCalhoun-Lopez |
| Categories | science electronics |
| Homepage | https://github.com/verilator/verilator |
| Platforms | darwin |
| Variants |
|
"verilator" depends on
build (7)
lib (2)
Ports that depend on "verilator"
No ports
Port Health:
Loading Port Health
Installations (30 days)
1
Requested Installations (30 days)
1
Livecheck results
verilator seems to have been updated (port version: 5.028, new version: 5.034)
livecheck ran: 1 day, 14 hours ago