verilator (science/verilator) Updated: 1 year, 5 months ago Add to my watchlist
Verilog compiler and simulatorVerilator is a Verilog compiler and simulator.
Version: 5.028 License: (LGPL-3 or Artistic-2)
GitHub
206 build(s) found
Page 3 of 3 | Showing build(s) 201 to 206
| Builder | Build Number | Start Time | Elapsed Time | Watcher | Build Status |
|---|---|---|---|---|---|
| 10.12 | 93456 | 2019-06-15 15:27:21 | 0:06:09 | 24372 | build successful |
| 10.13 | 58787 | 2019-06-15 15:27:00 | 0:04:20 | 16349 | build successful |
| 10.10 | 88894 | 2019-06-15 15:26:49 | 0:05:29 | 25428 | build successful |
| 10.14 | 32962 | 2019-06-15 15:25:59 | 0:04:23 | 7063 | build successful |
| 10.11 | 88376 | 2019-06-15 15:25:40 | 0:04:13 | 25382 | build successful |
| 10.9 | 91008 | 2019-06-15 15:25:21 | 0:03:38 | 25374 | build successful |