{"name":"vbs","portdir":"science/vbs","version":"1.4.0","license":"GPL-2+","platforms":"darwin","epoch":0,"replaced_by":null,"homepage":"http://www.flex.com/~jching/","description":"Verilog Behavioral Simulator","long_description":"This is the public release of the Verilog Behavioral Simulator. Verilog is a Hardware Description Language used mostly for digital circuit design and simulation. This program is a simple implementation of a Verilog simulator. VBS tries to implement all of the Verilog behavioral constructs that are synthesizable, but still allow complex test vectors for simulation.","active":true,"categories":["science"],"maintainers":[],"variants":["universal"],"dependencies":[{"type":"build","ports":["clang-9.0"]}],"depends_on":[]}