{"name":"iverilog","portdir":"science/iverilog","version":"20250103","license":"GPL-2+","platforms":"darwin","epoch":0,"replaced_by":null,"homepage":"http://iverilog.icarus.com/","description":"Icarus Verilog","long_description":"Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called \"vvm\") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format.","active":true,"categories":["science"],"maintainers":[{"name":"degnan.68k","github":"bpdegnan","ports_count":6},{"name":"mark","github":"markemer","ports_count":114}],"variants":[],"dependencies":[{"type":"build","ports":["clang-17","bison","gperf","libtool","autoconf","automake"]},{"type":"lib","ports":["zlib","readline","bzip2"]}],"depends_on":[{"type":"lib","ports":["qucs"]}]}